IP vendors (vendors of intellectual property (IP) cores) and other source of design information currently focus their development efforts on designs for the application-specific integrated circuit (ASIC) market. This is due, in large part, to the simple, reliable methods that are presently available to determine revenues. These methods allow an IP vendor to determine per-chip IP royalties on the ASICs manufactured using their designs.
IP vendors do not tailor their IP cores for use in programmable logic devices (PLDs) such as Field Programmable Gate Arrays (FPGAs) or Complex Programmable Logic Devices (CPLDs), because there is presently no method to identify (and/or restrict) which PLDs are allowed to incorporate the vendor's IP core(s). As a result, IP vendors lack the motivation necessary to optimize their designs for a given PLD architecture. ASIC-centric IP cores therefore typically perform poorly in a PLD, which further reinforces the need for designers and manufacturers to migrate to an ASIC-based approach quickly after initial prototype testing using PLDs.
What is therefore desired is a technique that provides a per-chip royalty method for third-party IP cores that can be used in a PLD such as an FPGA. Such a technique should prevent access to/use of the subject IP cores by unauthorized parties, and provide a significant cost-performance enhancement for PLD-based systems by allowing per-chip royalties to be determined, in a simple, convenient manner. Moreover, such a technique should provide IP vendors an incentive to optimize for a given PLD architecture by providing the foregoing features in a transparent, controllable, and economic mechanism. Such techniques should also allow for the ready identification of PLDs employing the technique.